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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. advance information for pre-production products; subject to change without notice. UCC20225-q1 slusdc2 ? november 2018 UCC20225 -q1 isolated dual-channel gate driver with single input in lga for automotive 48v systems 1 1 features 1 ? single pwm input, dual output ? resistor-programmable dead time ? 4-a peak source, 6-a peak sink output ? cmti greater than 100-v/ns ? switching parameters: ? 19-ns typical propagation delay ? 5-ns maximum delay matching ? 6-ns maximum pulse-width distortion ? 3-v to 18-v input vcci range ? rejects input transients shorter than 5-ns ? fast disable for power sequencing ? ttl and cmos compatible inputs ? 5-mm x 5-mm space-saving lga-13 package ? safety-related certifications: ? 3535-v pk isolation per vde v 0884-11:2017 ? 2500-v rms isolation for 1 minute per ul 1577 ? cqc certification per gb4943.1-2011 ? aec q100 qualified with: ? device temperature grade 1 ? device hbm esd classification level h2 ? device cdm esd classification level c6 2 applications ? automotive external audio amplifier ? automotive 48v systems 3 description the UCC20225 -q1 is an single-input, dual-output isolated gate driver with 4-a source and 6-a sink peak current in 5-mm x 5-mm lga-13. it is designed to drive power transistors up to 5-mhz with best-in- class propagation delay and pulse-width distortion. the input side is isolated from the two output drivers by a 2.5-kv rms isolation barrier, with minimum 100- v/ns common-mode transient immunity (cmti). internal functional isolation between the two output- side drivers allows working voltage up to 700-v dc . the UCC20225 -q1 allows programmable dead time (dt) through a resistor on dt pin. a disable pin shuts down both outputs simultaneously when it is set high, and allows normal operation when left open or grounded. the device accepts vdd supply voltages up to 25-v. a wide vcci range from 3-v to 18-v makes the driver suitable for interfacing with both analog and digital controllers. all the supply voltage have under voltage lock-out (uvlo) protection. with all these advanced features, the UCC20225 -q1 enables high power density, high efficiency, and robustness in a variety of automotive applications. device information (1) part number package body size (nom) UCC20225 -q1 npl lga (13) 5 mm 5 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. functional block diagram 9 8 10 driver vddb outb vssb uvlo demod mod 12 11 13 driver vdda outa vssa uvlo demod mod functional isolation isolation barrier 2 4,7 1 6 5 3 gnd dt nc dis pwm vcci copyright ? 2017, texas instruments incorporated disable, uvlo and deadtime advance information tools & software technical documents ordernow productfolder support &community
2 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 5 6.5 power ratings ........................................................... 5 6.6 insulation specifications ............................................ 6 6.7 safety-related certifications ..................................... 7 6.8 safety limiting values .............................................. 7 6.9 electrical characteristics ........................................... 8 6.10 switching characteristics ........................................ 9 6.11 thermal derating curves ........................................ 9 6.12 typical characteristics .......................................... 11 7 parameter measurement information ................ 15 7.1 propagation delay and pulse width distortion ....... 15 7.2 rising and falling time ......................................... 15 7.3 pwm input and disable response time ................ 15 7.4 programable dead time ........................................ 16 7.5 power-up uvlo delay to output ........................ 16 7.6 cmti testing ........................................................... 17 8 detailed description ............................................ 18 8.1 overview ................................................................. 18 8.2 functional block diagram ....................................... 18 8.3 feature description ................................................. 19 8.4 device functional modes ........................................ 22 9 application and implementation ........................ 24 9.1 application information ............................................ 24 9.2 typical application .................................................. 24 10 power supply recommendations ..................... 35 11 layout ................................................................... 36 11.1 layout guidelines ................................................. 36 11.2 layout example .................................................... 37 12 device and documentation support ................. 39 12.1 documentation support ....................................... 39 12.2 certifications ......................................................... 39 12.3 receiving notification of documentation updates 39 12.4 community resources .......................................... 39 12.5 trademarks ........................................................... 39 12.6 electrostatic discharge caution ............................ 39 12.7 glossary ................................................................ 39 13 mechanical, packaging, and orderable information ........................................................... 39 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. date revision notes nov 2018 * advance information release. advance information
3 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) p =power, g= ground, i= input, o= output 5 pin configuration and functions npl package 13-pin lga top view pin functions pin i/o (1) description name no. disable 5 i disables both driver outputs if asserted high, enables if set low or left open. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. bypass using a 1nf low esr/esl capacitor close to dis pin when connecting to a micro controller with distance. dt 6 i programmable dead time function. tying dt to vcci disables the dt function with dead time 0ns. placing a resistor (r dt ) between dt and gnd adjusts dead time according to: dt (in ns) = 10 x r dt (in k ). it is recommended to parallel a ceramic capacitor, 2.2nf or above, close to dt pin to achieve better noise immunity when using r dt . gnd 1 g primary-side ground reference. all signals in the primary side are referenced to this ground. nc 3 ? no internal connection. outa 12 o output of driver a. connect to the gate of the a channel fet or igbt. output a is in phase with pwm input with a propagation delay outb 9 o output of driver b. connect to the gate of the b channel fet or igbt. output b is always complementary to output a with a programmed dead time. pwm 2 i pwm input has a ttl/cmos compatible input threshold. this pin is pulled low internally if left open. vcci 4 p primary-side supply voltage. locally decoupled to gnd using a low esr/esl capacitor located as close to the device as possible. vcci 7 p this pin is internally shorted to pin 4. preference should be given to bypassing pin-4 to pin-1 instead of pin-7 to pin-1. vdda 13 p secondary-side power for driver a. locally decoupled to vssa using a low esr/esl capacitor located as close to the device as possible. vddb 10 p secondary-side power for driver b. locally decoupled to vssb using a low esr/esl capacitor located as close to the device as possible. vssa 11 g ground for secondary-side driver a. ground reference for secondary side a channel. vssb 8 g ground for secondary-side driver b. ground reference for secondary side b channel. advance information not to scale 1 gnd 2 pwm 3 nc 4 vcci 5 disable 6 dt 7 vcci 8 vssb 9 outb 10 vddb 11 vssa 12 outa 13 vdda
4 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) to maintain the recommended operating conditions for t j , see the thermal information . 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit input bias pin supply voltage vcci to gnd ? 0.3 20 v driver bias supply vdda-vssa, vddb-vssb ? 0.3 30 v output signal voltage outa to vssa, outb to vssb ? 0.3 v vdda +0.3, v vddb +0.3 v outa to vssa, outb to vssb, transient for 200 ns ? 2 v vdda +0.3, v vddb +0.3 v input signal voltage pwm, dis, dt to gnd ? 0.3 v vcci +0.3 v pwm transient for 50ns ? 5 v vcci +0.3 v channel to channel voltage vssa-vssb, vssb-vssa 700 v junction temperature, t j (2) ? 40 150 c storage temperature, t stg ? 65 150 c (1) aec q100-002 indicates that hbm stressing shall be in accordance with the ansi/esda/jedec js-001 specification. 6.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per aec q100-002 (1) 4000 v charged-device model (cdm), per aec q100-011 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min max unit vcci vcci input supply voltage 3 18 v vdda, vddb driver output bias supply 9.2 25 v t a ambient temperature ? 40 125 c t j junction temperature ? 40 130 c advance information
5 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953 . (2) standard jesd51-9 area array smt test board (2s2p) in still air, with 12-mil dia. 1-oz copper vias connecting vssa and vssb to the plane immediately below (three vias for vssa, three vias for vssb). 6.4 thermal information thermal metric (1) UCC20225 -q1 unit lga (13) (2) r ja junction-to-ambient thermal resistance 98.0 c/w r jc(top) junction-to-case (top) thermal resistance 48.8 r jb junction-to-board thermal resistance 78.9 jt junction-to-top characterization parameter 26.2 jb junction-to-board characterization parameter 76.8 6.5 power ratings value unit p d power dissipation by UCC20225 -q1 vcci = 18 v, vdda/b = 12 v, pwm = 3.3 v, 3.5 mhz 50% duty cycle square wave 1-nf load 1.25 w p di power dissipation by primary side of UCC20225 - q1 0.05 p da , p db power dissipation by each driver side of UCC20225 -q1 0.60 advance information
6 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated (1) creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. creepage and clearance on a printed-circuit board become equal in certain cases. techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications. (2) package dimension tolerance 0.05mm. (3) this coupler is suitable for basic electrical insulation only within the maximum operating ratings. compliance with the safety ratings shall be ensured by means of suitable protective circuits. (4) testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier. (5) apparent charge is electrical discharge caused by a partial discharge (pd). (6) all pins on each side of the barrier tied together creating a two-pin device. 6.6 insulation specifications parameter test conditions value unit clr external clearance (1) (2) shortest pin-to-pin distance through air 3.5 mm cpg external creepage (1) shortest pin-to-pin distance across the package surface 3.5 mm dti distance through the insulation minimum internal gap (internal clearance) > 21 m cti comparative tracking index din en 60112 (vde 0303-11); iec 60112 > 600 v material group i overvoltage category per iec 60664-1 rated mains voltage 150 v rms i-iii rated mains voltage 300 v rms i-ii din v vde v 0884-11 (vde v 0884-11): 2017-01 (3) v iorm maximum repetitive peak isolation voltage ac voltage (bipolar) 792 v pk v iowm maximum working isolation voltage ac voltage (sine wave); time dependent dielectric breakdown (tddb) test; (see figure 1 ) 560 v rms dc voltage 792 v dc v iotm maximum transient isolation voltage v test = v iotm , t = 60 s (qualification); v test = 1.2 v iotm , t = 1 s (100% production) 3535 v pk v iosm maximum surge isolation voltage (4) test method per iec 62368-1, 1.2/50 s waveform, v test = 1.3 v iosm (qualification) 3500 v pk q pd apparent charge (5) method a, after input/output safety test subgroup 2/3, v ini = v iotm , t ini = 60s; v pd(m) = 1.2 v iorm , t m = 10s < 5 pc method a, after environmental tests subgroup 1, v ini = v iotm , t ini = 60s; v pd(m) = 1.2 v iorm , t m = 10s < 5 method b1; at routine test (100% production) and preconditioning (type test) v ini = 1.2 v iotm ; t ini = 1 s; v pd(m) = 1.5 v iorm , t m = 1s < 5 c io barrier capacitance, input to output (6) v io = 0.4 sin (2 ft), f =1 mhz 1.2 pf r io isolation resistance, input to output v io = 500 v at t a = 25 c > 10 12 v io = 500 v at 100 c t a 125 c > 10 11 v io = 500 v at t s =150 c > 10 9 pollution degree 2 climatic category 40/125/21 ul 1577 v iso withstand isolation voltage v test = v iso = 3000 v rms , t = 60 sec. (qualification), v test = 1.2 v iso = 3000v rms , t = 1 sec (100% production) 2500 v rms advance information
7 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.7 safety-related certifications vde ul cqc certified according to din v vde v 0884-11:2017-01 recognized under ul 1577 component recognition program certified according to gb 4943.1- 2011 basic insulation maximum transient overvoltage, 3535 v pk ; maximum repetitive peak voltage, 792 v pk ; maximum surge isolation voltage, 2719 v pk single protection, 2500 v rms basic insulation, altitude 5000 m, tropical climate 320-v rms maximum working voltage certification number: 40016131 certification number: e181974 certification number: cqc18001186974 (1) the maximum safety temperature, t s , has the same value as the maximum junction temperature, t j , specified for the device. the i s and p s parameters represent the safety current and safety power respectively. the maximum limits of i s and p s should not be exceeded. these limits vary with the ambient temperature, t a . the junction-to-air thermal resistance, r ja , in the thermal information table is that of a device installed on a high-k test board for leaded surface-mount packages. use these equations to calculate the value for each parameter: t j = t a + r ja p, where p is the power dissipated in the device. t j(max) = t s = t a + r ja p s , where t j(max) is the maximum allowed junction temperature. p s = i s v i , where v i is the maximum input voltage. 6.8 safety limiting values safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. parameter test conditions side min typ max unit i s safety output supply current (1) r ja = 98.0 o c/w, vdda/b = 12 v, t a = 25 c, t j = 150 c see figure 2 driver a, driver b 50 ma r ja = 98.0 o c/w, vdda/b = 25 v, t a = 25 c, t j = 150 c driver a, driver b 24 ma p s safety supply power (1) r ja = 98.0 o c/w, t a = 25 c, t j = 150 c see figure 3 input 0.05 w driver a 0.60 driver b 0.60 total 1.25 t s safety temperature (1) 150 c advance information
8 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.9 electrical characteristics v vcci = 3.3 v or 5 v, 0.1- f capacitor from vcci to gnd, v vdda = v vddb = 12 v, 1- f capacitor from vdda and vddb to vssa and vssb, t a = ? 40 c to +125 c, (unless otherwise noted) parameter test conditions min typ max unit supply currents i vcci vcci quiescent current disable = vcci 1.5 2.0 ma i vdda , i vddb vdda and vddb quiescent current disable = vcci 1.0 1.8 ma i vcci vcci operating current (f = 500 khz) current per channel, c out = 100 pf 2.5 ma i vdda , i vddb vdda and vddb operating current (f = 500 khz) current per channel, c out = 100 pf 2.5 ma vcci supply undervoltage lockout thresholds v vcci_on rising threshold vcci_on 2.55 2.7 2.85 v v vcci_off falling threshold vcci_off 2.35 2.5 2.65 v v vcci_hys threshold hysteresis 0.2 v vdd supply undervoltage lockout thresholds v vdda_on, v vddb_on rising threshold vdda_on, vddb_on 8.3 8.7 9.2 v v vdda_off, v vddb_off falling threshold vdda_off, vddb_off 7.8 8.2 8.7 v v vdda_hys, v vddb_hys threshold hysteresis 0.5 v pwm and disable v pwmh , v dish input high voltage 1.6 1.8 2 v v pwml , v disl input low voltage 0.8 1 1.2 v v pwm_hys , v dis_hys input hysteresis 0.8 v v pwm negative transient, ref to gnd, 50 ns pulse not production tested, bench test only ? 5 v output i oa+ , i ob+ peak output source current c vdd = 10 f, c load = 0.18 f, f = 1 khz, bench measurement 4 a i oa- , i ob- peak output sink current c vdd = 10 f, c load = 0.18 f, f = 1 khz, bench measurement 6 a r oha , r ohb output resistance at high state i out = ? 10 ma, t a = 25 c, r oha , r ohb do not represent drive pull- up performance. see t rise in switching characteristics and output stage for details. 5 r ola , r olb output resistance at low state i out = 10 ma, t a = 25 c 0.55 v oha , v ohb output voltage at high state v vdda , v vddb = 12 v, i out = ? 10 ma, t a = 25 c 11.95 v v ola , v olb output voltage at low state v vdda , v vddb = 12 v, i out = 10 ma, t a = 25 c 5.5 mv deadtime and overlap programming dead time pull dt pin to vcci 0 ns dt pin is left open, min spec characterized only, tested for outliers 8 15 ns r dt = 20 k 160 200 240 ns advance information
9 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.10 switching characteristics v vcci = 3.3 v or 5 v, 0.1- f capacitor from vcci to gnd, v vdda = v vddb = 12 v, 1- f capacitor from vdda and vddb to vssa and vssb, t a = ? 40 c to +125 c, (unless otherwise noted). parameter test conditions min typ max unit t rise output rise time, 20% to 80% measured points c out = 1.8 nf 6 16 ns t fall output fall time, 90% to 10% measured points c out = 1.8 nf 7 12 ns t pwmin minimum pulse width output off for less than minimum, c out = 0 pf 20 ns t pdhl propagation delay from inx to outx falling edges 14 19 30 ns t pdlh propagation delay from inx to outx rising edges 14 19 30 ns t pwd pulse width distortion |t pdlh ? t pdhl | 6 ns t dm propagation delays matching between vouta, voutb 5 ns |cm h | high-level common-mode transient immunity pwm is tied to gnd or vcci; v cm =1200v; (see cmti testing ) 100 v/ns |cm l | low-level common-mode transient immunity 100 6.11 thermal derating curves figure 1. isolation capacitor life time projection advance information stress voltage (v rms ) 0 500 1000 1500 2000 2500 3000 3500 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 1.e+8 1.e+9 1.e+10 20% safety margin zone: 672 v rms , 26 years operating zone: 560 v rms , 20 years 1.e+0 life time (sec)
10 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated thermal derating curves (continued) figure 2. thermal derating curve for safety-related lim iting current (current in each channel with both channels running simultaneously) figure 3. thermal derating curve for safety-related limiting power ambient temperature (c) safety limiting current per channel (ma) 0 50 100 150 200 0 10 20 30 40 50 60 d002 vdd = 12v vdd = 25v ambient temperature (c) safety limiting power (mw) 0 50 100 150 200 0 250 500 750 1000 1250 1500 d003 advance information
11 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 6.12 typical characteristics vdda = vddb= 12 v, vcci = 3.3 v, t a = 25 c, no load unless otherwise noted. figure 4. per channel current consumption vs. frequency (no load, vdd = 12 v or 25 v) figure 5. per channel current consumption (i vdda/b ) vs. frequency (1-nf load, vdd = 12 v or 25 v) figure 6. per channel current consumption (i vdda/b ) vs. frequency (10-nf load, vdd = 12 v or 25 v) figure 7. per channel (i vdda/b ) supply current vs. temperature (no load, different switching frequencies) figure 8. per channel (i vdda/b ) quiescent supply current vs temperature (no load, input low, no switching) figure 9. i vcci quiescent supply current vs temperature (no load, dis is high, no switching) frequency (khz) current (ma) 10 25 40 55 70 85 100 0 6 12 18 24 30 d001 vdd= 12v vdd= 25v temperature ( q c) vdd current (ma) -40 -20 0 20 40 60 80 100 120 140 160 0 1 2 3 4 5 6 d001 50khz 250khz 500khz 1mhz temperature ( q c) current (ma) -40 -20 0 20 40 60 80 100 120 140 0 0.4 0.8 1.2 1.6 2 d001 vdd= 12v vdd= 25v temperature ( q c) current (ma) -40 -20 0 20 40 60 80 100 120 140 1 1.2 1.4 1.6 1.8 2 d001 vcci= 3.3v vcci= 5v advance information frequency (khz) current (ma) 0 500 1000 1500 2000 2500 3000 0 10 20 30 40 50 d001 vdd= 12v vdd= 25v frequency (khz) current (ma) 0 800 1600 2400 3200 4000 4800 5600 0 4 8 12 16 20 d001 vdd=12v vdd=25v
12 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb= 12 v, vcci = 3.3 v, t a = 25 c, no load unless otherwise noted. figure 10. rising and falling times vs. load (vdd = 12 v) figure 11. output resistance vs. temperature figure 12. propagation delay vs. temperature figure 13. propagation delay vs. vcci figure 14. pulse width distortion vs. temperature figure 15. propagation delay matching (t dm ) vs. vdd load (nf) time (ns) 0 2 4 6 8 10 0 5 10 15 20 25 d001 t rise t fall temperature ( q c) propagation delay (ns) -40 -20 0 20 40 60 80 100 120 140 8 12 16 20 24 28 d001 rising edge (t pdlh ) falling edge (t pdhl ) vcci (v) propagation delay (ns) 3 6 9 12 15 18 15 16 17 18 19 20 d001 rising edge (t pdlh ) falling edge (t pdhl ) vdda/b (v) propagation delay matching (ns) 10 13 16 19 22 25 -5 -2.5 0 2.5 5 d001 rising edge falling edge advance information temperature ( q c) pulse width distortion (ns) -40 -20 0 20 40 60 80 100 120 140 -5 -3 -1 1 3 5 d001 temperature ( q c) resistance ( : ) -40 -20 0 20 40 60 80 100 120 140 0 2 4 6 8 10 d001 output pull-up output pull-down
13 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb= 12 v, vcci = 3.3 v, t a = 25 c, no load unless otherwise noted. figure 16. propagation delay matching (t dm ) vs. temperature figure 17. vdd uvlo hysteresis vs. temperature figure 18. vdd uvlo threshold vs. temperature figure 19. pwm/dis hysteresis vs. temperature figure 20. pwm/dis low threshold figure 21. pwm/dis high threshold temperature ( q c) uvlo threshold (v) -40 -20 0 20 40 60 80 100 120 140 5 6 7 8 9 10 d001 v vdda_on v vdda_off temperature ( q c) pwm/dis threshold hysterisis (mv) -40 -20 0 20 40 60 80 100 120 140 700 740 780 820 860 900 d001 vcc=3.3v vcc=5v vcc=12v temperature ( q c) propagation delay matching (ns) -40 -20 0 20 40 60 80 100 120 140 -5 -2.5 0 2.5 5 d001 rising edge falling edge temperature ( q c) hysterisis (mv) -40 -20 0 20 40 60 80 100 120 140 450 470 490 510 530 550 d001 advance information temperature ( q c) in/dis low threshold (v) -40 -20 0 20 40 60 80 100 120 140 0.9 0.96 1.02 1.08 1.14 1.2 d001 vcc=3.3v vcc= 5v vcc=12v temperature ( q c) in/dis high threshold (v) -40 -20 0 20 40 60 80 100 120 140 1.6 1.68 1.76 1.84 1.92 2 d001 vcc=3.3v vcc= 5v vcc=12v
14 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical characteristics (continued) vdda = vddb= 12 v, vcci = 3.3 v, t a = 25 c, no load unless otherwise noted. figure 22. dead time vs. temperature (with r dt = 20 k and 100 k ) figure 23. dead time matching vs. temperature (with r dt = 20 k and 100 k ) temperature ( q c) dead time (ns) -40 -20 0 20 40 60 80 100 120 140 0 300 600 900 1200 1500 d001 r dt = 20k : r dt = 100k : temperature ( q c) ' dt (ns) -40 -20 0 20 40 60 80 100 120 140 -50 -39 -28 -17 -6 5 d001 r dt = 20k : r dt = 100k : advance information
15 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7 parameter measurement information 7.1 propagation delay and pulse width distortion figure 24 shows how to calculate pulse width distortion (t pwd ) and delay matching (t dm ) from the propagation delays of channels a and b. these parameters can be measured by disabling the dead time function by shorting the dt pin to vcc. figure 24. propagation delay matching and pulse width distortion 7.2 rising and falling time figure 25 shows the criteria for measuring rising (t rise ) and falling (t fall ) times. for more information on how short rising and falling times are achieved see output stage . figure 25. rising and falling time criteria 7.3 pwm input and disable response time figure 26 shows the response time of the disable function. for more information, see disable pin . figure 26. disable pin timing advance information outb outa 90% 90% t pdhlb pwm t pdhla t dm-f = | t pdhla ? w pdhlb | t pdlhb 10% t pdlha t dm-r = | t pdlha ? w pdlhb | t pwd = | t pdlha/b ? w pdhla/b | 20% t rise 80% 90% 10% t fall pwm dis outa 10% 10% dis low response time dis high response time 90%
16 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.4 programable dead time tying it to gnd through an appropriate resistor (r dt ) sets a dead-time interval. for more details on dead time, refer to programmable dead time (dt) pin . figure 27. dead-time switching parameters 7.5 power-up uvlo delay to output before the driver is ready to deliver a proper output state, there is a power-up delay from the uvlo rising edge to output and it is defined as t vcci+ to out for vcci uvlo (typically 40- s) and t vdd+ to out for vdd uvlo (typically 50- s). it is recommended to consider proper margin before launching pwm signal after the driver's vcci and vdd bias supply is ready. figure 28 and figure 29 show the power-up uvlo delay timing diagram for vcci and vdd. if pwm are active before vcci or vdd have crossed above their respective on thresholds, the output will not update until t vcci+ to out or t vdd+ to out after vcci or vdd crossing its uvlo rising threshold. however, when either vcci or vdd receive a voltage less than their respective off thresholds, there is < 1 s delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. this asymmetric delay is designed to ensure safe operation during vcci or vdd brownouts. figure 28. vcci power-up uvlo delay figure 29. vdda/b power-up uvlo delay dead time (with r dt1 ) dead time (with r dt2 ) t pdhl outb pwm 10% 90% 90% 10% t pdhl outa vcci, inx vddx v vdd_on outx t vdd+ to out v vdd_off vcci, inx vddx v vcci_on outx v vcci_off t vcci+ to out advance information
17 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 7.6 cmti testing figure 30 is a simplified diagram of the cmti testing configuration. figure 30. simplified cmti testing setup 9 8 10 vddb outb vssb 12 11 13 vdda outa vssa functional isolation isolation barrier input logic 6 2 7 5 4 1 vcci dt dis gnd vcci pwm copyright ? 2017, texas instruments incorporated outb outa vss common mode surge generator gnd vdd vcc vcc advance information
18 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8 detailed description 8.1 overview there are several instances where controllers are not capable of delivering sufficient current to drive the gates of power transistors. this is especially the case with digital controllers, since the input signal from the digital controller is often a 3.3-v logic signal capable of only delivering a few ma. in order to switch power transistors rapidly and reduce switching power losses, high-current gate drivers are often placed between the output of control devices and the gates of power transistors. the UCC20225 -q1 is a flexible dual gate driver which can be configured to fit a variety of power supply and motor drive topologies, as well as drive several types of transistors, including sic mosfets. UCC20225 -q1 has many features that allow it to integrate well with control circuitry and protect the gates it drives such as: resistor- programmable dead time (dt) control, a disable pin, and under voltage lock out (uvlo) for both input and output voltages. the UCC20225 -q1 also holds its outa low when the pwm is left open or when the pwm pulse is not wide enough. the driver input pwm is cmos and ttl compatible for interfacing to digital and analog power controllers alike. importantly, channel a is in phase with pwm input and channel b is always complimentary with channel a with programmed dead time. 8.2 functional block diagram 9 8 10 driver vddb outb vssb uvlo demod mod 12 11 13 driver vdda outa vssa uvlo demod mod functional isolation isolation barrier deadtime control 2 4,7 1 6 5 3 gnd dt nc dis pwm vcci copyright ? 2017, texas instruments incorporated 200 k : 200 k : uvlo vcci pwm pwm advance information
19 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3 feature description 8.3.1 vdd, vcci, and under voltage lock out (uvlo) the UCC20225 -q1 has an internal under voltage lock out (uvlo) protection feature on the supply circuit blocks between the vdd and vss pins for both outputs. when the vdd bias voltage is lower than v vdd_on at device start-up or lower than v vdd_off after start-up, the vdd uvlo feature holds the effected outputs low, regardless of the status of the input pin (pwm). when the output stages of the driver are in an unbiased or uvlo condition, the driver outputs are held low by an active clamp circuit that limits the voltage rise on the driver outputs (illustrated in figure 31 ). in this condition, the upper pmos is resistively held off by r hi-z while the lower nmos gate is tied to the driver output through r clamp . in this configuration, the output is effectively clamped to the threshold voltage of the lower nmos device, typically around 1.5v, when no bias power is available. the clamp sinking current is limited only by the per- channel safety supply power, the ambient temperature, and the 6a peak sink current rating. figure 31. simplified representation of active pull down feature the vdd uvlo protection has a hysteresis feature (v vdd_hys ). this hysteresis prevents chatter when there is ground noise from the power supply. this also allows the device to accept small drops in bias voltage, which occurs when the device starts switching and operating current consumption increases suddenly. the input side of the UCC20225 -q1 also has an internal under voltage lock out (uvlo) protection feature. the device isn't active unless the voltage at vcci exceeds v vcci_on . a signal will cease to be delivered when vcci receives a voltage less than v vcci_off . as with the uvlo for vdd, there is hystersis (v vcci_hys ) to ensure stable operation. if pwm is active before vcci or vdd have crossed above their respective on thresholds, the output will not update until 50 s (typical) after vcci or vdd crossing its uvlo rising threshold. however, when either vcci or vdd receive a voltage less than their respective uvlo off thresholds, there is < 1 s delay, depending on the voltage slew rate on the supply pins, before the outputs are held low. this asymmetric delay is designed to ensure safe operation during vcci or vdd brownouts. advance information r hi_z vdd r clamp out vss r clamp is activated during uvlo output control
20 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated feature description (continued) the UCC20225 -q1 can withstand an absolute maximum of 30 v for vdd, and 20 v for vcci. table 1. UCC20225 -q1 vcci uvlo feature logic condition input outputs pwm outa outb vcci-gnd < v vcci_on during device start up h l l vcci-gnd < v vcci_on during device start up l l l vcci-gnd < v vcci_off after device start up h l l vcci-gnd < v vcci_off after device start up l l l table 2. UCC20225 -q1 vdd uvlo feature logic condition input outputs pwm outa outb vdd-vss < v vdd_on during device start up h l l vdd-vss < v vdd_on during device start up l l l vdd-vss < v vdd_off after device start up h l l vdd-vss < v vdd_off after device start up l l l (1) " x " means l, h or left open. (2) dis pin disables both driver outputs if asserted high, enables if set low or left open. this pin is pulled low internally if left open. it is recommended to tie this pin to ground if not used to achieve better noise immunity. bypass using a 1nf low esr/esl capacitor close to dis pin when connecting to a c with distance. 8.3.2 input and output logic table assume vcci, vdda, vddb are powered up. see vdd, vcci, and under voltage lock out (uvlo) for more information on uvlo operation modes. table 3. input/output logic table (1) input disable (2) outputs note pwm outa outb l or left open l or left open l h output transitions occur after the dead time expires. see programmable dead time (dt) pin h l or left open h l x h l l - 8.3.3 input stage the input pins (pwm and dis) of UCC20225 -q1 are based on a ttl and cmos compatible input-threshold logic that is totally isolated from the vdd supply voltage. the input pins are easy to drive with logic-level control signals (such as those from 3.3-v micro-controllers), since UCC20225 -q1 has a typical high threshold (v pwmh ) of 1.8 v and a typical low threshold of 1 v, which vary little with temperature (see figure 20 , figure 21 ). a wide hysteresis (v pwm_hys ) of 0.8 v makes for good noise immunity and stable operation. if any of the inputs are ever left open, internal pull-down resistors force the pin low. these resistors are typically 200 k (see functional block diagram ). however, it is still recommended to ground an input if it is not being used for improved noise immunity. since the input side of UCC20225 -q1 is isolated from the output drivers, the input signal amplitude can be larger or smaller than vdd, provided that it doesn ? t exceed the recommended limit. this allows greater flexibility when integrating with control signal sources, and allows the user to choose the most efficient vdd for any gate. that said, the amplitude of any signal applied to pwm must never be at a voltage higher than vcci. advance information
21 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.4 output stage the UCC20225 -q1 ? s output stages features a pull-up structure which delivers the highest peak-source current when it is most needed, during the miller plateau region of the power-switch turn on transition (when the power switch drain or collector voltage experiences dv/dt). the output stage pull-up structure features a p-channel mosfet and an additional pull-up n-channel mosfet in parallel. the function of the n-channel mosfet is to provide a brief boost in the peak-sourcing current, enabling fast turn on. this is accomplished by briefly turning on the n-channel mosfet during a narrow instant when the output is changing states from low to high. the on- resistance of this n-channel mosfet (r nmos ) is approximately 1.47- when activated. the r oh parameter is a dc measurement and it is representative of the on-resistance of the p-channel device only. this is because the pull-up n-channel device is held in the off state in dc condition and is turned on only for a brief instant when the output is changing states from low to high. therefore the effective resistance of the UCC20225 -q1 pull-up stage during this brief turn-on phase is much lower than what is represented by the r oh parameter, yielding a faster turn-on. the turn-on phase output resistance is the parallel combination r oh ||r nmos . the pull-down structure in UCC20225 -q1 is simply composed of an n-channel mosfet. the r ol parameter, which is also a dc measurement, is representative of the impedance of the pull-down state in the device. both outputs of the UCC20225 -q1 are capable of delivering 4-a peak source and 6-a peak sink current pulses. the output voltage swings between vdd and vss provides rail-to-rail operation, thanks to the mos-out stage which delivers very low drop-out. figure 32. output stage vdd out vss pull up shoot- through prevention circuitry input signal r oh r ol r nmos advance information
22 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 8.3.5 diode structure in UCC20225 -q1 figure 33 illustrates the multiple diodes involved in the esd protection components of the UCC20225 -q1. this provides a pictorial representation of the absolute maximum rating for the device. figure 33. esd structure 8.4 device functional modes 8.4.1 disable pin setting the disable pin high shuts down both outputs simultaneously. grounding (or left open) the disable pin allows UCC20225 -q1 to operate normally. the disable response time is in the range of 20ns and quite responsive, which is as fast as propagation delay. the disable pin is only functional (and necessary) when vcci stays above the uvlo threshold. it is recommended to tie this pin to ground if the disable pin is not used to achieve better noise immunity. 8.4.2 programmable dead time (dt) pin UCC20225 -q1 allows the user to adjust dead time (dt) in the following ways: 8.4.2.1 tying the dt pin to vcc if dt pin is tied to vcc, dead time function between outa and outb is disabled and the dead time between the two output channels is around 0ns. 2 5 6 pwm dis dt 20 v 20 v 1 gnd 4,7 vcci 30 v 12 11 30 v 10 9 vddb outb outa vssa 8 13 vssb vdda advance information
23 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated device functional modes (continued) 8.4.2.2 dt pin left open or connected to a programming resistor between dt and gnd pins if the dt pin is left open, the dead time duration (t dt ) is set to < 15-ns. it is not recommended to leave dt pin open for noisy environment. one can program t dt by placing a resistor, r dt , between the dt pin and gnd. the appropriate r dt value can be determined from equation 1 , where r dt is in k ? and t dt in ns: (1) the steady state voltage at dt pin is around 0.8v, and the dt pin current will be less than 10ua when r dt =100- k . since the dt pin current is used internally to set the dead time, and this current decreases as r dt increases, it is recommended to parallel a ceramic capacitor, 2.2-nf or above, close to dt pin to achieve better noise immunity and better dead time matching between two channels, especially when the dead time is larger than 300-ns. the input signal ? s falling edge activates the programmed dead time for the output. an output signal's dead time is always set to the driver ? s programmed dead time. the driver dead time logic is illustrated in figure 34 : figure 34. input and output logic relationship with dead time advance information dt dt t 10 r ? pwm outa outb dt
24 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the UCC20225 -q1 effectively combines both isolation and buffer-drive functions. the flexible, universal capability of the UCC20225 -q1 (with up to 18-v vcci and 25-v vdda/vddb) allows the device to be used as a low-side, high-side, high-side/low-side or half-bridge driver for mosfets, igbts or sic mosfets. with integrated components, advanced protection features (uvlo, dead time, and disable) and optimized switching performance, the UCC20225 -q1 enables designers to build smaller, more robust designs for enterprise, telecom, automotive, and industrial applications with a faster time to market. 9.2 typical application the circuit in figure 35 shows a reference design with UCC20225 -q1 driving a typical half-bridge configuration which could be used in several popular power converter topologies such as synchronous buck, synchronous boost, half-bridge/full bridge isolated topologies, and 3-phase motor drive applications. figure 35. typical application schematic advance information 9 8 10 vddb outb vssb 12 11 13 vdda outa vssa functional isolation isolation barrier input logic 6 3 2 7 5 4 1 copyright ? 2017, texas instruments incorporated c boot c vdd vss r off r on r gs r off r on c in vdd r boot vdd hv dc-link sw vcci dt dis gnd vcci pwm r dt r dis p c c vcc c in r in disable vcc vcc pwm analog or digital r gs c dt ? 2.2nf nc c dis
25 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated typical application (continued) 9.2.1 design requirements table 4 lists reference design parameters for the example application: UCC20225 -q1 driving 700-v mosfets in a high side-low side configuration. table 4. UCC20225 -q1 design requirements parameter value units power transistor ipb65r150cfd - vcc 5.0 v vdd 12 v input signal amplitude 3.3 v switching frequency (f s ) 200 khz dc link voltage 400 v 9.2.2 detailed design procedure 9.2.2.1 designing pwm input filter it is recommended that users avoid shaping the signals to the gate driver in an attempt to slow down (or delay) the signal at the output. however, a small input r in -c in filter can be used to filter out the ringing introduced by non-ideal layout or long pcb traces. such a filter should use an r in in the range of 0- to 100- and a c in between 10-pf and 100-pf. in the example, an r in = 51- and a c in = 33-pf are selected, with a corner frequency of approximately 100-mhz. when selecting these components, it is important to pay attention to the trade-off between good noise immunity and propagation delay. 9.2.2.2 select external bootstrap diode and its series resistor the bootstrap capacitor is charged by vdd through an external bootstrap diode every cycle when the low side transistor turns on. charging the capacitor involves high-peak currents, and therefore transient power dissipation in the bootstrap diode may be significant. conduction loss also depends on the diode ? s forward voltage drop. both the diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver circuit. when selecting external bootstrap diodes, it is recommended that one chose high voltage, fast recovery diodes or sic schottky diodes with a low forward voltage drop and low junction capacitance in order to minimize the loss introduced by reverse recovery and related grounding noise bouncing. in the example, the dc-link voltage is 800 v dc . the voltage rating of the bootstrap diode should be higher than the dc-link voltage with a good margin. therefore, a 600-v ultrafast diode, mura160t3g, is chosen in this example. a bootstrap resistor, r boot , is used to reduce the inrush current in d boot and limit the ramp up slew rate of voltage of vdda-vssa during each switching cycle, especially when the vssa(sw) pin has an excessive negative transient voltage. the recommended value for r boot is between 1 and 20 depending on the diode used. in the example, a current limiting resistor of 2.7 is selected to limit the inrush current of bootstrap diode. the estimated worst case peak current through d boot is, where ? v bdf is the estimated bootstrap diode forward voltage drop at 4 a. (2) dd bdf dboot (pk) boot v v 12 v 1.5 v i 4 a r 2.7 - - = = ? w advance information
26 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2.3 gate driver output resistor the external gate driver resistors, r on /r off , are used to: 1. limit ringing caused by parasitic inductances/capacitances. 2. limit ringing caused by high voltage/current switching dv/dt, di/dt, and body-diode reverse recovery. 3. fine-tune gate drive strength, i.e. peak sink and source current to optimize the switching loss. 4. reduce electromagnetic interference (emi). as mentioned in output stage , the UCC20225 -q1 has a pull-up structure with a p-channel mosfet and an additional pull-up n-channel mosfet in parallel. the combined peak source current is 4 a. therefore, the peak source current can be predicted with: (3) where ? r on : external turn-on resistance. ? r gfet_int : power transistor internal gate resistance, found in the power transistor datasheet. ? i o+ = peak source current ? the minimum value between 4 a, the gate driver peak source current, and the calculated value based on the gate drive loop resistance. (4) in this example: (5) (6) therefore, the high-side and low-side peak source current is 2.2 a and 2.5 a respectively. similarly, the peak sink current can be calculated with: (7) where ? r off : external turn-off resistance. ? v gdf : the anti-parallel diode forward voltage drop which is in series with r off . the diode in this example is an mss1p4. ? i o- : peak sink current ? the minimum value between 6 a, the gate driver peak sink current, and the calculated value based on the gate drive loop resistance. (8) dd bdf oa nmos oh on gfet _ int v v 12 v 1.3 v i 2.2 a r r r r 1.47 5 2.2 1.5 + - - = = ? + + w w + w + w dd ob nmos oh on gfet _ int v i min 4a, r r r r + ? ? = ? ? + + ? dd bdf oa nmos oh on gfet _ int v v i min 4a, r r r r + ? ? - = ? ? + + ? dd gdf ob ol off on gfet _ int v v i min 6a, r r r r - ? ? - = ? ? + + ? dd bdf gdf oa ol off on gfet _ int v v v i min 6a, r r r r - ? ? - - = ? ? + + ? dd ob nmos oh on gfet _ int v 12 v i 2.5 a r r r r 1.47 5 2.2 1.5 + = = ? + + w w + w + w advance information
27 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated in this example, (9) (10) therefore, the high-side and low-side peak sink current is 5.1 a and 5.5 a respectively. importantly, the estimated peak current is also influenced by pcb layout and load capacitance. parasitic inductance in the gate driver loop can slow down the peak gate drive current and introduce overshoot and undershoot. therefore, it is strongly recommended that the gate driver loop should be minimized. on the other hand, the peak source/sink current is dominated by loop parasitics when the load capacitance (c iss ) of the power transistor is very small (typically less than 1 nf), because the rising and falling time is too small and close to the parasitic ringing period. 9.2.2.4 estimate gate driver power loss the total loss, p g , in the gate driver subsystem includes the power losses of the UCC20225 -q1 (p gd ) and the power losses in the peripheral circuitry, such as the external gate drive resistor. bootstrap diode loss is not included in p g and not discussed in this section. p gd is the key power loss which determines the thermal safety-related limits of the UCC20225 -q1, and it can be estimated by calculating losses from several components. the first component is the static power loss, p gdq , which includes quiescent power loss on the driver as well as driver self-power consumption when operating with a certain switching frequency. p gdq is measured on the bench with no load connected to outa and outb at a given vcci, vdda/vddb, switching frequency and ambient temperature. figure 4 shows the per output channel current consumption vs. operating frequency with no load. in this example, v vcci = 5 v and v vdd = 12 v. the current on each power supply, with pwm switching from 0 v to 3.3 v at 200 khz is measured to be i vcci = 2 ma, and i vdda = i vddb = 1.5 ma. therefore, the p gdq can be calculated with (11) the second component is switching operation loss, p gdo , with a given load capacitance which the driver charges and discharges the load during each switching cycle. total dynamic loss due to load switching, p gsw , can be estimated with where ? q g is the gate charge of the power transistor. (12) if a split rail is used to turn on and turn off, then vdd is the total difference between the positive rail to the negative rail. so, for this example application: (13) gsw p 2 12 v 100 nc 200 khz 480 mw = = dd bdf gdf oa ol off on gfet _ int v v v 12 v 0.8 v 0.75 v i 5.1 a r r r r 0.55 0 1.5 - - - - - = = ? + + w + w + w advance information dd gdf ob ol off on gfet _ int v v 12 v 0.75 v i 5.5 a r r r r 0.55 0 1.5 - - - = = ? + + w + w + w gdq vcci vcci vdda vdda vddb vddb p v i v i v i 46 mw = + + ? gsw dd g sw p 2 v q f =
28 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated q g represents the total gate charge of the power transistor switching 400 v at 14 a, and is subject to change with different testing conditions. the UCC20225 -q1 gate driver loss on the output stage, p gdo , is part of p gsw . p gdo will be equal to p gsw if the external gate driver resistances and power transistor internal resistances are 0 , and all the gate driver loss is dissipated inside the UCC20225 -q1. if there are external turn-on and turn-off resistance, the total loss will be distributed between the gate driver pull-up/down resistances, external gate resistances, and power transistor internal resistances. importantly, the pull-up/down resistance is a linear and fixed resistance if the source/sink current is not saturated to 4 a/6 a, however, it will be non-linear if the source/sink current is saturated. therefore, p gdo is different in these two scenarios. case 1 - linear pull-up/down resistor: (14) in this design example, all the predicted source/sink currents are less than 4 a/6 a, therefore, the UCC20225 -q1 gate driver loss can be estimated with: (15) case 2 - nonlinear pull-up/down resistor: where ? v outa/b (t) is the gate driver outa and outb pin voltage during the turn on and off period. in cases where the output is saturated for some time, this can be simplified as a constant current source (4 a at turn-on and 6 a at turn-off) charging/discharging a load capacitor. then, the v outa/b (t) waveform will be linear and the t r_sys and t f_sys can be easily predicted. (16) for some scenarios, if only one of the pull-up or pull-down circuits is saturated and another one is not, the p gdo will be a combination of case 1 and case 2, and the equations can be easily identified for the pull-up and pull- down based on the above discussion. total gate driver loss dissipated in the gate driver UCC20225 -q1, p gd , is: (17) which is equal to 127 mw in the design example. 9.2.2.5 estimating junction temperature the junction temperature (t j ) of the UCC20225 -q1 can be estimated with: where ? t c is the UCC20225 -q1 case-top temperature measured with a thermocouple or some other instrument, and ? jt is the junction-to-top characterization parameter from the thermal information table. (18) using the junction-to-top characterization parameter ( jt ) instead of the junction-to-case thermal resistance (r jc ) can greatly improve the accuracy of the junction temperature estimation. the majority of the thermal energy of most ics is released into the pcb through the package leads, whereas only a small percentage of the total energy is released through the top of the case (where thermocouple measurements are usually conducted). r jc can only be used effectively when most of the thermal energy is released through the case, such as with metal packages or when a heatsink is applied to an ic package. in all other cases, use of r jc will inaccurately estimate the true junction temperature. jt is experimentally derived by assuming that the amount of energy leaving through the top of the ic will be similar in both the testing environment and the application environment. as long as the recommended layout guidelines are observed, junction temperature estimates can be made accurately to within a few degrees celsius. for more information, see the semiconductor and ic package thermal metrics application report . gdo 5 1.47 480 mw 0.55 p 120 mw 2 5 1.47 2.2 1.5 0.55 0 1.5 ? ? w w w = + ? ? ? w w + w + w w + w + w ? oh nmos gsw ol gdo oh nmos on gfet _ int ol off on gfet _ int r r p r p 2 r r r r r r r r ? ? = + ? ? + + + + ? gd gdq gdo p p p 46 mw 120 mw 166 mw = + = + = ( ) r _ sys f _ sys a /b a /b t t gdo sw dd out out 0 0 p 2 f 4 a v v (t) dt 6 a v (t) dt = - + ? ? j c jt gd t t p = + y advance information
29 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2.6 selecting vcci, vdda/b capacitor bypass capacitors for vcci, vdda, and vddb are essential for achieving reliable performance. it is recommended that one choose low esr and low esl surface-mount multi-layer ceramic capacitors (mlcc) with sufficient voltage ratings, temperature coefficients and capacitance tolerances. importantly, dc bias on an mlcc will impact the actual capacitance value. for example, a 25-v, 1- f x7r capacitor is measured to be only 500 nf when a dc bias of 15 v dc is applied. 9.2.2.6.1 selecting a vcci capacitor a bypass capacitor connected to vcci supports the transient current needed for the primary logic and the total current consumption, which is only a few ma. therefore, a 50-v mlcc with over 100 nf is recommended for this application. if the bias power supply output is a relatively long distance from the vcci pin, a tantalum or electrolytic capacitor, with a value over 1 f, should be placed in parallel with the mlcc. 9.2.2.6.2 selecting a vdda (bootstrap) capacitor a vdda capacitor, also referred to as a bootstrap capacitor in bootstrap power supply configurations, allows for gate drive current transients up to 6 a, and needs to maintain a stable gate drive voltage for the power transistor. the total charge needed per switching cycle can be estimated with where ? q g : gate charge of the power transistor. ? i vdd : the channel self-current consumption with no load at 200khz. (19) therefore, the absolute minimum c boot requirement is: where ? v vdda is the voltage ripple at vdda, which is 0.5 v in this example. (20) in practice, the value of c boot is greater than the calculated value. this allows for the capacitance shift caused by the dc bias voltage and for situations where the power stage would otherwise skip pulses due to load transients. therefore, it is recommended to include a safety-related margin in the c boot value and place it as close to the vdd and vss pins as possible. a 50-v 1- f capacitor is chosen in this example. (21) to further lower the ac impedance for a wide frequency range, it is recommended to have bypass capacitor with a low capacitance value, in this example a 100 nf, in parallel with c boot to optimize the transient performance. note too large c boot can be detrimental. c boot may not be charged within the first few cycles and v boot could stay below uvlo. as a result, the high-side fet will not follow input signal commands for several cycles. also during initial c boot charging cycles, the bootstrap diode has highest reverse recovery current and losses. boot c 1 f = m total boot dda q 107.5 nc c 0.22 f v 0.5 v = = ? m d vdd total g sw i @ 200 khz (no load) 1.5 ma q q 100 nc 107.5 nc f 200 khz = + = + = advance information
30 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2.6.3 select a vddb capacitor chanel b has the same current requirements as channel a, therefore, a vddb capacitor (shown as c vdd in figure 35 ) is needed. in this example with a bootstrap configuration, the vddb capacitor will also supply current for vdda through the bootstrap diode. a 50-v, 10- f mlcc and a 50-v, 0.22- f mlcc are chosen for c vdd . if the bias power supply output is a relatively long distance from the vddb pin, a tantalum or electrolytic capacitor, with a value over 10 f, should be used in parallel with c vdd . 9.2.2.7 dead time setting guidelines for power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor is important for preventing shoot-through during dynamic switching. the UCC20225 -q1 dead time specification in the electrical table is defined as the time interval from 90% of one channel ? s falling edge to 10% of the other channel ? s rising edge (see figure 27 ). this definition ensures that the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing. however, this dead time setting may not reflect the dead time in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, dc-link switching voltage/current, as well as the input capacitance of the load transistor. here is a suggestion on how to select an appropriate dead time for UCC20225 -q1: where ? dt setting : UCC20225 -q1 dead time setting in ns, dt setting = 10 rdt(in k ? ). ? dt req : system required dead time between the real v gs signal of the top and bottom switch with enough margin, or zvs requirement. ? t f_sys : in-system gate turn-off falling time at worst case of load, voltage/current conditions. ? t r_sys : in-system gate turn-on rising time at worst case of load, voltage/current conditions. ? t d(on) : turn-on delay time, from 10% of the transistor gate signal to power transistor gate threshold. (22) in the example, dt setting is set to 250-ns. it should be noted that the UCC20225 -q1 dead time setting is decided by the dt pin configuration (see programmable dead time (dt) pin ), and it cannot automatically fine-tune the dead time based on system conditions. it is recommended to parallel a ceramic capacitor, 2.2-nf or above, close to dt pin to achieve better noise immunity and dead time matching. setting re q f _ sys r _ sys d(on) dt dt t t t = + + - advance information
31 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.2.8 application circuits with output stage negative bias when parasitic inductances are introduced by non-ideal pcb layout and long package leads (e.g. to-220 and to-247 type packages), there could be ringing in the gate-source drive voltage of the power transistor during high di/dt and dv/dt switching. if the ringing is over the threshold voltage, there is the risk of unintended turn-on and even shoot-through. applying a negative bias on the gate drive is a popular way to keep such ringing below the threshold. below are a few examples of implementing negative gate drive bias. figure 36 shows the first example with negative bias turn-off on the channel-a driver using a zener diode on the isolated power supply output stage. the negative bias is set by the zener diode voltage. if the isolated power supply, v a , is equal to 25 v, the turn-off voltage will be ? 5.1 v and turn-on voltage will be 25 v ? 5.1 v 20 v. the channel-b driver circuit is the same as channel-a, therefore, this configuration needs two power supplies for a half-bridge configuration, and there will be steady state power consumption from r z . figure 36. negative bias with zener diode on iso-bias power supply output 9 8 10 vddb outb vssb 12 11 13 vdda outa vssa functional isolation isolation barrier input logic 6 2 1 7 5 3 4 copyright ? 2017, texas instruments incorporated c a1 r off r on c in hv dc-link sw c a2 + v a r z v z = 5.1 v 25 v advance information
32 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated figure 37 shows another example which uses two supplies (or single-input-double-output power supply). power supply v a+ determines the positive drive output voltage and v a ? determines the negative turn-off voltage. the configuration for channel b is the same as channel a. this solution requires more power supplies than the first example, however, it provides more flexibility when setting the positive and negative rail voltages. figure 37. negative bias with two iso-bias power supplies advance information 9 8 10 vddb outb vssb 12 11 13 vdda outa vssa functional isolation isolation barrier input logic 6 2 1 7 5 3 4 copyright ? 2017, texas instruments incorporated c a1 r off r on c in hv dc-link sw c a2 + v a+ + v a-
33 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated the last example, shown in figure 38 , is a single power supply configuration and generates negative bias through a zener diode in the gate drive loop. the benefit of this solution is that it only uses one power supply and the bootstrap power supply can be used for the high side drive. this design requires the least cost and design effort among the three solutions. however, this solution has limitations: 1. the negative gate drive bias is not only determined by the zener diode, but also by the duty cycle, which means the negative bias voltage will change when the duty cycle changes. therefore, converters with a fixed duty cycle (~50%) such as variable frequency resonant converters or phase shift converters favor this solution. 2. the high side vdda-vssa must maintain enough voltage to stay in the recommended power supply range, which means the low side switch must turn-on or have free-wheeling current on the body (or anti-parallel) diode for a certain period during each switching cycle to refresh the bootstrap capacitor. therefore, a 100% duty cycle for the high side is not possible unless there is a dedicated power supply for the high side, like in the other two example circuits. figure 38. negative bias with single power supply and zener diode in gate drive path advance information 9 8 10 vddb outb vssb 12 11 13 vdda outa vssa functional isolation isolation barrier input logic 6 2 1 7 5 3 4 copyright ? 2017, texas instruments incorporated c boot c vdd vss c z v z r off r on r gs c z v z r off r on r gs c in vdd r boot vdd hv dc-link sw
34 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 9.2.3 application curves figure 39 and figure 40 shows the bench test waveforms for the design example shown in figure 35 under these conditions: vcc = 5 v, vdd = 12 v, f sw = 200 khz, v dc-link = 400 v. channel 1 (indigo): UCC20225 -q1 pwm pin signal. channel 2 (cyan): gate-source signal on the high side power transistor. channel 3 (magenta): gate-source signal on the low side power transistor. in figure 39 , pwm is sent a 3.3 v, 20% duty-cycle signal. the gate drive signals on the power transistor have a 250-ns dead time, shown in the measurement section of figure 39 . the dead time matching is 10-ns with the 250-ns dead time setting. note that with high voltage present, lower bandwidth differential probes are required, which limits the achievable accuracy of the measurement. figure 40 shows a zoomed-in version of the waveform of figure 39 , with measurements for propagation delay and rising/falling time. importantly, the output waveform is measured between the power transistors ? gate and source pins, and is not measured directly from the driver outa and outb pins. due to the split on and off resistors (r on , r off ), different sink and source currents, and the miller plateau, different rising (60, 120 ns) and falling time (25 ns) are observed in figure 40 . figure 39. bench test waveform for pwm and outa/b figure 40. zoomed-in bench-test waveform advance information
35 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 10 power supply recommendations the recommended input supply voltage (vcci) for UCC20225 -q1 is between 3-v and 18-v. the recommended output bias supply voltage (vdda/vddb) range is between 9.2-v to 25-v. the lower end of this bias supply range is governed by the internal under voltage lockout (uvlo) protection feature of each device. vdd and vcci should not fall below their respective uvlo thresholds for normal operation, or else gate driver outputs can become clamped low for > 50 s by the uvlo protection feature (for more information on uvlo see vdd, vcci, and under voltage lock out (uvlo) ). the upper end of the vdda/vddb range depends on the maximum gate voltage of the power device being driven by UCC20225 -q1, and should not exceed the recommended maximum vdda/vddb of 25-v. a local bypass capacitor should be placed between the vdd and vss pins, with a value of between 220 nf and 10 f for device biasing. it is further suggested that an additional 100-nf capacitor be placed in parallel with the device biasing capacitor for high frequency filtering. both capacitors should be positioned as close to the device as possible. low esr, ceramic surface mount capacitors are recommended. similarly, a bypass capacitor should also be placed between the vcci and gnd pins. given the small amount of current drawn by the logic circuitry within the input side of UCC20225 -q1, this bypass capacitor has a minimum recommended value of 100 nf. advance information
36 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11 layout 11.1 layout guidelines one must pay close attention to pcb layout in order to achieve optimum performance for the UCC20225 -q1. below are some key points. component placement: ? low-esr and low-esl capacitors must be connected close to the device between the vcci and gnd pins and between the vdd and vss pins to support high peak currents when turning on the external power transistor. ? to avoid large negative transients on the switch node vssa (hs) pin, the parasitic inductances between the source of the top transistor and the source of the bottom transistor must be minimized. ? it is recommended to place the dead time setting resistor, r dt , and its bypassing capacitor close to dt pin of UCC20225 -q1. ? it is recommended to bypass using a 1nf low esr/esl capacitor, c dis , close to dis pin when connecting to a c with distance. ? grounding considerations: ? it is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. this will decrease the loop inductance and minimize noise on the gate terminals of the transistors. the gate driver must be placed as close as possible to the transistors. ? pay attention to high current path that includes the bootstrap capacitor, bootstrap diode, local vssb- referenced bypass capacitor, and the low-side transistor body/anti-parallel diode. the bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode by the vdd bypass capacitor. this recharging occurs in a short time interval and involves a high peak current. minimizing this loop length and area on the circuit board is important for ensuring reliable operation. high-voltage considerations: ? to ensure isolation performance between the primary and secondary side, one should avoid placing any pcb traces or copper below the driver device. pcb cutting or scoring beneath the ic are not recommended, since this can severely exacerbate board warping and twisting issues. ? for half-bridge, or high-side/low-side configurations, where the channel a and channel b drivers could operate with a dc-link voltage up to 700 v dc , one should try to increase the creepage distance of the pcb layout between the high and low-side pcb traces. thermal considerations: ? a large amount of power may be dissipated by the UCC20225 -q1 if the driving voltage is high, the load is heavy, or the switching frequency is high (refer to estimate gate driver power loss for more details). proper pcb layout can help dissipate heat from the device to the pcb and minimize junction to board thermal impedance ( jb ). ? increasing the pcb copper connecting to vdda, vddb, vssa and vssb pins is recommended, with priority on maximizing the connection to vssa and vssb (see figure 42 and figure 43 ). however, high voltage pcb considerations mentioned above must be maintained. ? if there are multiple layers in the system, it is also recommended to connect the vdda, vddb, vssa and vssb pins to internal ground or power planes through multiple vias of adequate size. these vias should be located close to the ic pins to maximize thermal conductivity. however, keep in mind that there shouldn ? t be any traces/coppers from different high voltage planes overlapping. advance information
37 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 11.2 layout example figure 41 shows a 2-layer pcb layout example with the signals and key components labeled. figure 41. layout example figure 42 and figure 43 shows top and bottom layer traces and copper. note there are no pcb traces or copper between the primary and secondary side, which ensures isolation performance. advance information
38 UCC20225-q1 slusdc2 ? november 2018 www.ti.com product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated layout example (continued) pcb traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node vssa (sw), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling. figure 42. top layer traces and copper figure 43. bottom layer traces and copper figure 44 and figure 45 are 3d layout pictures with top view and bottom views. note the location of the pcb cutout between the primary side and secondary sides, which ensures isolation performance. figure 44. 3-d pcb top view figure 45. 3-d pcb bottom view advance information
39 UCC20225-q1 www.ti.com slusdc2 ? november 2018 product folder links: UCC20225-q1 submit documentation feedback copyright ? 2018, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.1.1 related documentation for related documentation see the following: ? isolation glossary 12.2 certifications ul online certifications directory, " fppt2.e181974 nonoptical isolating devices - component " certificate number: 20170718-e181974, vde pruf- und zertifizierungsinstitut certification , certificate of conformity with factory surveillance cqc online certifications directory, " gb4943.1-2011, digital isolator certificate " certificate number:cqc18001186974 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks e2e is a trademark of texas instruments. 12.6 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. advance information
package option addendum www.ti.com 21-nov-2018 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples pUCC20225qnpltq1 active vlga npl 13 250 tbd call ti call ti -40 to 125 UCC20225qnplrq1 preview vlga npl 13 3000 tbd call ti call ti -40 to 125 UCC20225qnpltq1 preview vlga npl 13 250 tbd call ti call ti -40 to 125 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) rohs: ti defines "rohs" to mean semiconductor products that are compliant with the current eu rohs requirements for all 10 rohs substances, including the requirement that rohs substance do not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, "rohs" products are suitable for use in specified lead-free processes. ti may reference these types of products as "pb-free". rohs exempt: ti defines "rohs exempt" to mean products that contain lead but are compliant with eu rohs pursuant to a specific eu rohs exemption. green: ti defines "green" to mean the content of chlorine (cl) and bromine (br) based flame retardants meet js709b low halogen requirements of <=1000ppm threshold. antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
package option addendum www.ti.com 21-nov-2018 addendum-page 2 other qualified versions of UCC20225-q1 : ? catalog: UCC20225 note: qualified version definitions: ? catalog - ti's standard catalog product
www.ti.com package outline c 2x 3.9 12x 0.65 (0.1) typ 13x 0.7 0.6 1 max 13x 0.35 0.25 2.075 4.15 b 5.1 4.9 a 5.1 4.9 (0.7) vlga - 1 max height npl0013a land grid array 4222800/b 04/2017 pin 1 index area 0.08 c seating plane 0.15 c a b 0.08 c 1 7 8 13 symm symm 0.15 c b a pin 1 id note 3 notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. pin 1 indicator is electrically connected to pin 1. 0.08 c scale 2.500
www.ti.com example board layout 13x (0.65) 0.07 max all around 0.07 min all around 13x (0.3) (4.15) 10x (0.65) (r0.05) typ vlga - 1 max height npl0013a land grid array 4222800/b 04/2017 symm symm 1 8 7 land pattern example 1:1 ratio with package solder pads scale:15x 13 notes: (continued) 4. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). metal solder mask opening non solder mask defined (preferred) solder mask details not to scale metal under solder mask solder mask opening solder mask defined
www.ti.com example stencil design 13x (0.65) 13x (0.3) 10x (0.65) (4.15) (r0.05) vlga - 1 max height npl0013a land grid array 4222800/b 04/2017 notes: (continued) 5. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 1 8 7 13 solder paste example based on 0.125 thick stencil scale:15x symm symm
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